PRASHANT
YOURAJ WANJARI.
Bangalore
|
leadershipstageprofile@gmail.com |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Objective:
To contribute in an institute of repute
in the position, this will let me learn while I can contribute to the organization
using my current knowledge and qualifications.
EDUCATION
QUALIFICATION:
M-Tech
from
IIT
Mumbai
|
IIT
Mumbai
2008-2011
|
CGPA 6.91 out of 10
|
B-Tech
from
NIT
Surat
|
NIT
Surat (ELECTRONICS)
2004-2008
|
CGPA 6.19 out of10
|
12th
from Kamala Nehru
Mahavidyalaya
Maharashtra
|
Maharashtra
State Board 2004
|
Percentage 78.67%
|
10th
from saroj high
school,maharastra
|
Maharashtra
State Board 2002
|
Percentage 70.53%
|
Work Experience :
Ø Worked for Reinfold Physical Innovation Labs
as a Embeded system design engineer from 1 August-2011
to 17 April at Bangalore
:
Professional Projects
Design of 8051 and
ARM 7 Development board for Renfold Physical Innovation lab
EDA Tools: Eagle
Role:
Designed 8051 and ARM 7 Development board for production
Generated test program for design
Made some RTOS for development board
Implementation
of FFT processor
HDL: VHDL
EDA Tools: Xilinx-ISE, Modelsim
Role:
Designed 4, 8, 16, 32, 64 and 128-point FFT processors.
Managed RTL design verification.
Outlined functional verification plans.
Generated test cases for design with test benches.
Simulated design and verified the results.
The design has been
synthesized and tested on Spartan-6 FPGA.
Documented design and verification results.
I2C Based memory Implementation
HDL: VHDL
EDA Tools:
Xilinx-ISE, Modelsim
Role:
Designed an I2C based EPROM.
Managed RTL design verification.
Outlined functional verification plans.
Generated test cases for design with test benches.
Simulated design and verified the results.
The design has been synthesized and tested on Spartan-3E FPGA.
Documented design and verification results.
Implementation of UART
HDL: VHDL
EDA Tools:
Xilinx-ISE, Modelsim
Role:
Designed UART .
Managed RTL design verification.
Outlined functional verification plans.
Generated test cases for design with test benches.
Simulated design and verified the results.
The design has been synthesized and tested on Spartan-3E FPGA.
Documented design and verification results.
Video Graphics Adaptor
HDL: VHDL
EDA Tools:
Xilinx-ISE, Modelsim
Role:
Designed Video graphics adapter.
Managed RTL design verification.
Outlined functional verification plans.
Generated test cases for design with test benches.
Simulated design and verified the results.
The design has been synthesized and tested on Spartan-3E FPGA.
ØWorked
as System administrator of VLSI Design Lab in IIT Mumbai from July 2008 to June
2011:
Area of
Expertise :
·
Installation
and maintenance of Linux and windows Operating system as well as software
inside OS in lab PC.
·
Installation
of CAD tool ,cadence 6.14 cadence 5.14 , Mentor Graphics, Model Sim, Synopsis, Xilinx,
cadence encounter in lab PC
·
Arrangement
of tutorial and training to beginner for above CAD tool
·
Creation
of account in Linux OS machine and its maintenance for Lab user.
·
Development
and maintenance of SMDP Website- http://www.ee.iitb.ac.in/~smdp/index.html
Field of Interest :
ASIC design, Digital VLSI Chip Design,
Device Design, Embedded System Design Using Microcontroller Analog VLSI Chip
Design, Radio Frequency Chip Design, Mixed
Signal VLSI Chip Design
Major Projects and Seminar :
·
M. Tech Project:
Design of High Speed Delta Sigma Analog to Digital Converter for WCDMA
Application using 0.18 um technology (Guide: Prof.
Arun.N.Chandorkar)
·
Operational
Amplifier: Two stage opamp with unity gain frequency 600 MHz
·
Non-Overlapping
clock generation circuit: Two phase non overlapping circuit
·
Clocked
Comparator: tested at 200 MHz
·
Switch:
cmos complementary switch
·
Biasing
circuit: four bias voltage (0.65V, 0.6997V, 1V, and 1.2V) for the operational
Amplifier,
CMFB, comparator
·
CMFB:
for differential OPAMP
·
First order delta sigma modulator: SNR
23.84 dB and SFDR 39dB
·
Second
order delta sigma modulator: SNR 31.73 dB and SFDR 46dB.
·
CIC
filter: Cascaded Integrators ,Divide by 3 clocks, Divide by 24 clocks Cascaded Comb,
Cascaded Integrated Comb filter and Layout of all blocks.
M.Tech
Seminar:
Ø Design of High speed Pipeline
Analog to Digital converter for Camera Application (Guide: Prof.
Arun.N.Chandorkar):
·
In
this seminar, I made literature survey of all analog to digital converter and
choose this A/D Design method for seminar
Skills :
·
C,
C++, HTML ,Shell scripting on Unix (Perl, bash)
·
Hardware
Description Languages:
VHDL, verilog
·
Assembly Languages:
8085, 8086, 89C51, ARM, PIC
·
Software Packages:
Cadence, Mat Lab, Latex, Spice, Model Sim, Xilinx, Synopsis, cadence
Encounter,
Eagle,Protius,
· Operating Systems,
Windows, Linux.
Personal Interests and Traits: Surfing, Enjoying meaningful electronic media entertainment,
interacting with different types of people for enhancing
communication/interpersonal skills and understanding of psychological and
philosophical aspects.
DECLARATION:
I
hereby declare that all the information
furnished above by me is true to the best of my knowledge and belief.
Prashant Youraj Wanjari
Bangalore
No comments:
Post a Comment